1. Field of the Invention
The present invention relates to the field of liquid crystal displaying, and in particular to a liquid crystal display drive circuit.
2. The Related Arts
The progress of science and technology and the improvement of living quality of human beings makes liquid crystal display devices widely used everywhere in daily living. People are now asking for more for the liquid crystal display devices and start demanding large display screen and fast response. However, increasing the size of the liquid crystal display brings more complicated wire lay-out. Also, accurately controlling pixel electrodes is getting more difficult due to wiring delay caused by the increase of number of pixel electrodes driven by a TFT (Thin-Film Transistor) substrate and feedback caused by the existence of TFT parasitic capacitor.
Referring to FIGS. 1 and 2, FIG. 1 is a schematic view showing the structure of a basic drive circuit of a TFT array substrate. In the drawing, pixel electrodes 100 are shown distributed in the entire TFT array substrate and each pixel electrode 100 is connected to a drain terminal d of at least one TFT. The source terminal s of each TFT is connected to at least one data line and a plurality data lines collectively constitutes a data bus structure. The gate terminal g of each TFT is connected to at least one gate line and a plurality of gate lines collectively constitutes a gate bus structure. The data bus and the gate bus collectively control data writing of the pixel electrodes via the thin-film transistors. The pixel electrode 100 of the ith column and jth row of the TFT array substrate is commonly controlled by the gate line G(j) and data line S(i). When a writing operation is performed on the pixel electrode P′(i,j), the gate line G(j) is set at a high level to set the thin-film transistor T(i,j) in a conducting state. Under this condition, the magnitude of the drive voltage applied through the data line S(i) causes the liquid crystal molecules neighboring a site opposing the pixel electrode 100 to rotate according to a predetermined rotation direction so as to achieve displaying of image. Such a writing operation is performed in row-wise manner, so that when the gate line G(j) is in the high level, all the pixel electrodes of the jth row can perform a writing operation.
Referring to FIG. 2, which is a schematic view showing connection of an equivalent drive circuit of each pixel electrode, the ith data line S(i) is connected to the source terminal s of the thin-film transistor T(i,j) at the ith column and jth row. The jth gate line G(j) is connected to the gate terminal g of the thin-film transistor T(i,j) at the ith column and jth row. The drain terminal d of the thin-film transistor T(i,j) at the ith column and jth row is connected to the pixel electrode 100 at the ith column and jth row. The symbol Cgd indicates a parasitic capacitor between the gate terminal g and the drain terminal d. The parasitic capacitor Cgd is inherent to the characteristics of the thin-film transistors. The symbol Clc indicates an equivalent capacitor of a liquid crystal layer between the TFT substrate and a CF (Color Filter) substrate and Cs is a compensation capacitor between the TFT substrate and Vcom. The compensation capacitor Cs is provided for compensating for voltage drop of the equivalent liquid crystal capacitor Clc through electrical discharging in order to properly extend the retention time for direction change of liquid crystal molecules in the area of the equivalent liquid crystal capacitor Clc. However, with the increase of the numbers of rows and columns of the pixel electrodes distributed in a matrix form on a TFT array substrate, the lengthened gate lines and data lines cause time delay in the drive circuit. As shown in FIG. 3, on the other hand, the parasitic capacitor Cgd existing between the gate terminal g and the drain terminal d of a thin-film transistor directly affects the gate voltage Vg controlling conduction and cutoff of the thin-film transistor, especially for the neighboring site of the pixel electrode that is located at a distal end away from the data bus circuit, where due to the influence of discharging voltage caused by the parasitic capacitors Cgd of the previous (n−1) thin-film transistors that the gate signal passed first and the influence caused by circuit delay, this site may have an extended response time and also suffers attenuation of gate voltage caused by the electrical discharging when the gate voltage goes from high to low, making the conduction time of the thin-film transistor T(n,j) extended from Tj by ΔTj. In other words, the thin-film transistor that is supposed to be cut off is abnormally conducted on. This makes the driving time of the pixel electrode P(n,j) connected to the drain terminal d of the thin-film transistor extended by ΔTdx, leading to abnormal rotation of the liquid crystal molecules neighboring the pixel electrode, which causes variation of transmittance and abnormality of contrast.